-- $Id: $
-- File name:   tb_OUTPUT_BLOCK.vhd
-- Created:     4/7/2011
-- Author:      Brandon Blaine Gardner
-- Lab Section: 337-06
-- Version:     1.0  Initial Test Bench

library ieee;
--library gold_lib;   --UNCOMMENT if you're using a GOLD model
use ieee.std_logic_1164.all;
--use gold_lib.all;   --UNCOMMENT if you're using a GOLD model

entity tb_OUTPUT_BLOCK is
generic (Period : Time := 41.6667 ns);
end tb_OUTPUT_BLOCK;

architecture TEST of tb_OUTPUT_BLOCK is

  function INT_TO_STD_LOGIC( X: INTEGER; NumBits: INTEGER )
     return STD_LOGIC_VECTOR is
    variable RES : STD_LOGIC_VECTOR(NumBits-1 downto 0);
    variable tmp : INTEGER;
  begin
    tmp := X;
    for i in 0 to NumBits-1 loop
      if (tmp mod 2)=1 then
        res(i) := '1';
      else
        res(i) := '0';
      end if;
      tmp := tmp/2;
    end loop;
    return res;
  end;

  component OUTPUT_BLOCK
    PORT(
         CLK : in std_logic;
         RST : in std_logic;
         EN : in std_logic;
         SYNC : in std_logic;
         STB : in std_logic;
         DATA : in std_logic_vector (15 downto 0);
         REQ : out std_logic;
         SDO : out std_logic
    );
  end component;

-- Insert signals Declarations here
  signal CLK : std_logic;
  signal RST : std_logic;
  signal EN : std_logic;
  signal SYNC : std_logic;
  signal STB : std_logic;
  signal DATA : std_logic_vector (15 downto 0);
  signal REQ : std_logic;
  signal SDO : std_logic;

-- signal <name> : <type>;

begin

CLKGEN: process
  variable CLK_tmp: std_logic := '0';
begin
  CLK_tmp := not CLK_tmp;
  CLK <= CLK_tmp;
  wait for Period/2;
end process;

  DUT: OUTPUT_BLOCK port map(
                CLK => CLK,
                RST => RST,
                EN => EN,
                SYNC => SYNC,
                STB => STB,
                DATA => DATA,
                REQ => REQ,
                SDO => SDO
                );

--   GOLD: <GOLD_NAME> port map(<put mappings here>);

process

  begin

-- Insert TEST BENCH Code Here

    RST <= '0';
    EN <= '0';
    SYNC <= '0';
    STB <= '0';
    DATA <= "0000000000000000";
    
    wait for Period;
    
    RST <= '1';
    
    wait for Period * 4;
    
    DATA <= "1010101010101010"; -- AAAA
    wait for Period;
    STB <= '1';
    wait for Period;
    STB <= '0';
    
    wait for Period / 2;
    
    EN <= '1';
    
    wait for Period * 6 / 4;
    wait for Period * 6;
    
    SYNC <= '1';
    wait for Period * 16;
    SYNC <= '0';
    
    wait for Period * 2;
    
    DATA <= x"ABCD"; -- 1010 1011 1100 1101 
    
    wait for Period ;
    STB <= '1';
    wait for Period ;
    STB <= '0';
    
    wait for Period * 16;
    
    DATA <= x"6666"; -- 0110 0110 ...
    
    wait for Period ;
    STB <= '1';
    wait for Period ;
    STB <= '0';
    
    wait;

  end process;
end TEST;
